1. Field
Example embodiments relate to a method of forming a pattern for a semiconductor device and a method of forming a charge storage pattern using the same. Other example embodiments relate to a non-volatile memory device including a charge storage pattern and methods of manufacturing the same. Other example embodiments relate to a method of forming a pattern having a smaller and/or more uniform thickness.
2. Description of the Related Art
Semiconductor memory devices, in general, are classified as either volatile or non-volatile memory devices. Volatile memory devices (e.g., dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices) may have relatively higher input/output (I/O) speeds and lose data stored therein when power is shut off. Non-volatile memory devices (e.g., read-only memory (ROM) devices) maintain data stored therein even when power is shut off. Among the non-volatile memory devices, electrically erasable programmable ROM (EEPROM) devices or flash memory devices are higher in demand. Particularly, the flash memory device is a kind of an advanced EEPROM device in which data may be erased at a relatively high speed. In the flash memory device, data which is electrically stored may be programmed or erased through a Fowler-Nordheim (F-N) tunneling mechanism and/or a channel hot electron injection mechanism.
Flash memory devices may be classified, in general, as a NAND type and a NOR type. NOR flash memory devices may have higher operation speeds. NAND flash memory devices have a higher degree of integration.
The NAND flash memory device requires that the programming and erasing of the data be performed in a short time at as low a voltage as possible. As such, each unit cell of the NAND flash memory device needs to have a substantially high coupling ratio.
For increasing the coupling ratio of the NAND flash memory device, the electrical capacitance between the floating gate and the control gate needs to be higher and/or the electrical capacitance between the floating gate and the substrate needs to be lower in a unit cell of the NAND flash memory device.
A line width and a gap distance in the gate pattern needs to be smaller in a unit cell of the NAND flash memory device in order to increase the degree of integration of the NAND flash memory device.
A conventional dielectric layer includes a multilayer structure in which a silicon oxide layer, a silicon nitride layer and a silicon oxide layer may be sequentially stacked between the floating gate pattern and the control gate pattern in a flash memory device. It is desirable that the floating gate pattern, which the dielectric layer contacts, has a substantially large surface area so as to increase the capacitance between the floating gate pattern and the control gate pattern. As such, the floating gate pattern may be formed with a substantially. large line width The dielectric layer may be formed even on a sidewall of the floating gate pattern.
If the floating gate pattern has a substantially large thickness and a small gap distance, a parasitic capacitance may rapidly increase between neighboring floating gate patterns causing interference between neighboring unit cells. The neighboring floating gate patterns may be frequently coupled electrically. As such, programming of a first unit cell unintentionally causes programming of a second unit cell adjacent to the first unit cell, which in turn unintentionally increases the threshold voltage of the second unit cell. The unit cells may be spaced apart from each other by a desired distance in order to prevent (or reduce) interference between neighboring unit cells. The large gap space between the unit cells requires a large surface area for the unit cell, decreasing the degree of integration of the NAND flash memory device.
In order to address the above problems, a metal oxide having a higher dielectric constant is used as the dielectric layer. If the dielectric constant of the dielectric layer is substantially high, the dielectric layer may have a larger capacitance although the surface area of the floating gate pattern is decreased. As such, the line width and height of the floating gate pattern may be decreased and the degree of integration of the flash memory device may be increased. The relatively small height of the floating gate pattern reduces the parasitic capacitance between the neighboring floating gate patterns.
As described above, operation characteristics of the NAND flash memory device may increase due to the reduction of the pattern height of the floating gate. It may be difficult to form the floating gate pattern with a smaller height.
Hereinafter, the height of the pattern may be described (or referred to) as a thickness of the pattern for the convenience of understanding, and thus the small height of the pattern means (or includes) a thin pattern and a large height of the pattern means (or includes) a thick pattern.
If the floating gate pattern has a non-uniform thickness, the coupling ratio is different at each pair of the neighboring unit cells. A non-uniform coupling ratio in a flash memory device usually causes an operation failure of the device. As such, it is desirable to have a floating gate pattern with a substantially uniform height for operation reliability. It may be difficult to form a floating gate pattern having a more uniform and thin thickness on the entire surface of a substrate in view of the manufacturing process.
It may be desirable to form gate patterns with a substantially large thickness despite the smaller thickness of the floating gate patterns. For example, the gate patterns of a selection transistor, which is located at a marginal portion of cell transistor chains of a flash memory device, and of a transistor, which is in a peripheral region of a substrate, may have a substantially large thickness even though the floating gate patterns of the other transistors have a substantially small thickness. It may be difficult to form only the floating gate pattern with a substantially small thickness while the gate patterns of the selection transistor and the peripheral transistor are formed with a substantially large thickness.